1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to redundancy of a serial access memory portion in a frame buffer memory.
2. Description of the Background Art
FIG. 2 is a block diagram showing a configuration of a serial access memory portion in a conventional frame buffer memory.
Referring to FIG. 2, the frame buffer memory includes a memory cell array (not shown) for storing a plurality of data, 4.times.m sense amplifiers 11-14, 4.times.m transfer gates 31-34, m data registers 20, and m pairs of transfer gates 40a, 40b.
Four sense amplifiers 11-14, four transfer gates 31-34, one data register 20, and one pair of transfer gates 40a, 40b configure each of normal units N1-Nm.
Respective sense amplifiers 11-14 amplify and hold data D1-D4 read out from the memory cell array. Respective transfer gates 31-34 transfer data between a corresponding one of sense amplifiers 11-14 and data register 20 in response to a corresponding one of control signals CS1-CS4. These data is transferred through a data transfer line 38.
Data register 20 can hold data temporarily. A pair of transfer gates 40a, 40b transfers data between data register 20 and data buses 42a, 42b in response to select signals SE1-SEm.
The frame buffer memory further includes one redundancy unit Rp configured similar to normal units N1-Nm. The redundancy unit Rp includes four redundancy sense amplifiers 51-54, four redundancy transfer gates 61-64, one redundancy data register 60, and one pair of redundancy transfer gates 70a, 70b.
Respective sense amplifiers 51-54 amplify and hold data DR1-DR4 read out from a redundancy portion of the memory cell array. Respective transfer gates 61-64 transfer data between a corresponding one of sense amplifiers 51-54 and a redundancy data register 60 in response to a corresponding one of four control signals CS1-CS4. These data is transferred through a redundancy data transfer line 68.
Redundancy data register 60 can hold data temporarily. A pair of redundancy transfer gates 70a, 70b transfers data between redundancy data register 60 and redundancy data buses 72a, 72b in response to a redundancy select signal SER.
The frame buffer memory further includes a serial selector 80. In normal operation, that is, when correct data is read out from all data registers 20 in normal units N1-Nm, serial selector 80 sequentially selects data registers 20 in normal units N1-Nm to read out data from the selected data register 20 to data buses 42a, 42b, or to write data from data buses 42a, 42b to data register 20.
On the other hand, in abnormal operation, that is, when correct data is not read out from data registers 20 in normal units N1-Nm, serial selector 80 selects redundancy data register 60 instead of data register 20 to read out data from redundancy data register 60 to redundancy data buses 72a, 72b, or to write data from redundancy data buses 72a, 72b to redundancy data register 60.
Operation of the serial access memory portion will now be described.
In normal operation, 4.times.m data D1-D4 read out from the memory cell array is amplified and held by sense amplifiers 11-14.
When control signal CS1 rises to a logical high or H level, m transfer gates 31 corresponding to the signal are rendered conductive. When control signal CS2 rises to the H level, m transfer gates 32 corresponding to the signal are rendered conductive. When control signal CS3 rises to the H level, m transfer gates 33 corresponding to the signal are rendered conductive. Similarly, when control signal CS4 rises to the H level, m transfer gates 34 corresponding to the signal are rendered conductive. As a result, in each of normal units N1-Nm, a corresponding one of sense amplifiers 11-14 and data register 20 are connected each other, and data is transferred from the corresponding one of sense amplifiers 11-14 to data register 20 through data transfer line 38.
In each of normal units N1-Nm, four sense amplifiers 11-14 are connected to one data register 20 through four transfer gates 31-34. Therefore, data in these sense amplifiers 11-14 is selectively transferred to one data register 20 in response to four control signals CS1-CS4.
After data is transferred to data register 20, select signals SE1-SEm from serial selector 80 rise to the H level sequentially. In response to select signals SE1-SEm attaining the H level, a corresponding transfer gate pair 40a, 40b is rendered conductive. Data is transferred from data register 20 to data buses 42a, 42b through transfer gate pair 40a, 40b, and further provided externally.
The description will now be given of the case where data is not correct which is read out from one data register 20 in normal units N1-Nm.
When data is not correct which is transferred from a memory cell to data register 20 through sense amplifier 13 and transfer gate 33 in normal unit N1, for example, correct data is stored in advance in, instead of the memory cell, a memory cell corresponding to sense amplifier 53 in the redundancy unit Rp.
As in the above normal operation, data from the memory cell array is amplified and held by 4.times.m sense amplifiers 11-14 and four redundancy sense amplifiers 51-54.
When any one of four control signals CS1-CS4 rises to the H level, either of m transfer gates 31, m transfer gates 32, m transfer gates 33 or m transfer gates 34 corresponding to the control signal and a corresponding one of redundancy transfer gates 61-64 are rendered conductive. When control signal CS3 rises to the H level, for example, m transfer gates 33 and one redundancy transfer gate 63 are rendered conductive. As a result, in each of normal units N1-Nm, data is transferred from sense amplifier 13 to data register 20 through transfer gate 33. In the redundancy unit Rp, data is transferred from redundancy sense amplifier 53 to redundancy data register 60 through redundancy transfer gate 63.
In this case, data transferred to data register 20 in normal unit N1 is not correct. However, correct data is transferred to redundancy data register 60 instead.
Then, select signals SE1-SEm from serial selector 80 rise to the H level sequentially. In this case, redundancy select signal SER rises to the H level instead of select signal SE1. More specifically, after redundancy select signal SER rises to the H level, select signal SE2 (not shown)--select signal SEm rise to the H level sequentially.
When redundancy select signal SER rises to the H level, data in redundancy data register 60 is transferred to redundancy data buses 72a, 72b through a pair of redundancy transfer gates 70a, 70b, and further provided externally. Then, when select signals SE2-SEm rise to the H level sequentially, data in corresponding data register 20 is transferred to data buses 42a, 42b through a pair of transfer gates 40a, 40b, and further provided externally.
As described above, in the serial access memory portion including the redundancy unit Rp, even if data read out from normal units N1-Nm is not correct, by storing correct data in a predetermined memory cell, the correct data is read out from the redundancy unit Rp.
As described above, in a conventional serial access memory portion, the redundancy unit Rp having the same configuration as normal units N1-Nm is arranged. This is because it is impossible to predict which of four control signals CS1-CS4 at the H level causes erroneous data to be read out from normal units N1-Nm.
However, when erroneous data is read out from normal units N1-Nm only in response to the H level of one of four control signals CS1-CS4, for example, three of four redundancy sense amplifiers 51-54 are wasted. When erroneous data is read out from normal units N1-Nm in response to the H level of two of four control signals CS1-CS4, two of four redundancy sense amplifiers 51-54 are wasted.